Design of Low-Power SRAM Cell in 45nm Technology
Proposes a modified 8T SRAM cell topology to reduce leakage power and improve read stability at 45nm, validated through SPICE simulation across process corners.
- Project code
- AUX-VLSI-504
- Domain
- VLSI & Electronics
- Type
- Hardware project
- Level · Year
- Advanced · 2025-26
Technologies and components
What is included
- Working hardware prototype
- Circuit and block diagrams
- Source code with comments
- Project report (college format)
- PPT for review and viva
- Demo and viva support
More VLSI & Electronics Projects
Low-Power VLSI Design of 8-Bit ALU using CMOS
Designs and simulates an 8-bit arithmetic logic unit at the transistor level in 180nm CMOS technology, comparing power-delay product agai…
View project →VLSI & Electronics · AdvancedFPGA-Based Digital Signal Processing for Audio Filtering
Implements FIR and IIR filter architectures on an FPGA to remove noise from live audio streams in real time, benchmarking latency against…
View project →VLSI & Electronics · AdvancedVLSI Implementation of AES Encryption Core
A pipelined 128-bit AES encryption core is synthesised on FPGA hardware, evaluating throughput and resource utilisation against software-…
View project →Frequently asked questions
Can I get the Design of Low-Power SRAM Cell in 45nm Technology project for my final year?
Yes. This project (code AUX-VLSI-504) is available as a hardware project kit for the 2025-26 academic year. Contact us on WhatsApp to request it.
Can this project be customised?
Yes. Features, technology and documentation can be modified to suit your guide and college requirements.
Which departments is this project suitable for?
ECE, EEE, EIE and Mechatronics students, and CSE students interested in IoT or embedded work.
Get this project with full support
Ask about customisation, delivery time and viva support.
